Ron 30 + years in Electronic Design. RF to Digital, 9 + years in Signal Integrity Several years in EMI/EMC/ESD ADS frequency domain/time domain simulation, " Touchstone/Libra/Spice PCB parameter extraction using TDR w/TDA and VNA PCB Design Analysis PCB Design Analysis Bob A talented PCB Layout Specialist with twenty five years of experience Cadence Advanced Package Designer, Allegro and Concept HDL Protel99SE * CAMtastic * PC-Gerber * AutoCAD (R12/R14/2000) PADS PowerPCB 5.0 and BlazeRouter * P-CAD * OrCAD HTML * Microsoft Office (Word, Excel, PowerPoint) Sam Over Five years in Signal Integrity Engineering, Modeling of semiconductor and packaging System-level Characterization PHD –Microelectronics Characterization, Product Testing & Validation; Signal Integrity> ADS and Hspice MSEE - Microwave Sue PSPICE, QuickSimII, ModelSim, Eldo, SimpleScalar 3.0, Matla Verilog HDL MIPS MSEE – EE John VCS and Verilog Hi-Speed Interconnect Modeling (S param. and VNA), Speed2000, Specctraquest – Allegro, HSpice, Apsim RLGC 2d field solver, Chronology TimingDesigner. VNA, spectrum analyzers, VMEbus analyzers, TDR, BERT Steve 20+ years experience emphasis on Signal Integrity. interconnect modeling of packages and connectors. crosstalk, timing analysis,